What We Offer

• Scan Insertion & ATPG: Test coverage, fault modeling
• Memory BIST: Built-in self-test implementation
• JTAG & Boundary Scan: IEEE 1149.1 standard
• DFT Automation: Using industry-standard EDA tools

Training Highlights

• Industry Tools: Synopsys DFT Compiler, Cadence Modus
• Fault Simulation: Stuck-at, transition, path delay faults
• Low Power Test Techniques: Power-aware testing strategies
• Hands-on Experience: Practical case studies & projects

Training Duration

📅 Duration: 4 to 6 Weeks (Flexible Scheduling Available)

Who Should Attend?

• DFT Engineers
• VLSI Design & Test Engineers
• ASIC Verification Engineers