What You Will Learn

• Physical Design Flow: Floor Planning, Power Planning
• Clock Tree Synthesis (CTS): Timing & Power Optimization
• Place & Route: Standard Cells, Routing Optimization
• Sign-Off Analysis: STA, IR Drop, LVS, DRC

Internship Highlights

• Live Projects: ASIC Tape-Out, Real-World Challenges
• Industry Standard Tools: Cadence Innovus, Synopsys ICC2
• Expert Mentorship: Learn from VLSI Professionals
• Certification: Upon Successful Completion

Internship Duration

📅 Duration: 3 to 6 Months (Flexible Scheduling Available)

Who Can Apply?

• Electronics & VLSI Students
• ASIC/FPGA Enthusiasts
• Fresh Graduates Looking for Hands-on Experience