What We Offer

• Floorplanning & Placement: Hierarchical design, congestion analysis
• Clock Tree Synthesis (CTS): Skew optimization, timing analysis
• Routing: Global & detailed routing, DRC fixing
• Signoff & Optimization: IR drop, ECO, STA analysis

Training Highlights

• Industry Tools: Cadence Innovus, Synopsys ICC2, Mentor Graphics
• Static Timing Analysis (STA): Timing closure techniques
• Power & IR Drop Analysis: Power planning & optimization
• Hands-on Learning: Real-time projects & case studies

Training Duration

📅 Duration: 4 to 6 Weeks (Flexible Scheduling Available)

Who Should Attend?

• Physical Design Engineers
• VLSI Enthusiasts
• ASIC Backend Engineers